The present invention relates to a layout synthesis technique of a LSI leaf cell such as a standard cell or a data pass leaf cell to be used for an electric circuit such as a CMOS'LSI, and more particularly to a method for determining placement of transistors in a cell area.
In recent years, a semiconductor process technology has been developed at the dizzying pace, and technological innovations have been made successively. Every time design and development of the most advanced high-performance system are projected in response to the technological innovations of a process, it is necessary to develop a new cell library. At the same time, there are various semiconductor processes. Each process is utilized according to use. For this reason, the cell library should also be prepared corresponding to the various processes. Also in design of a LSI system, high-speed operation, low power consumption and the like are targeted. The cell library should correspond to the various targets. In other words, the cell library has recently been developed very often. Actually, a great number of cells should be prepared for one library. Furthermore, a submicron era has began so that a mask design rule (design rule) has been complicated still more. Consequently, a reality with the development of the cell library has become more serious.
In development of a standard cell library and a private cell library for a data pass according to the prior art, layout design thereof has been obtained most manually. The reason is that a cell having a high degree of integration should be designed because the area of a leaf cell directly influences that of a block and furthermore that of a chip. In consideration of the reality related to the development of the cell library, it is apparent that manual layout design will not meet the needs of development in the near future. Accordingly, the cell layout synthesis technique will become more important rapidly.
Cell layout synthesis (cell synthesis) means that a mask layout having a transistor level is generated from a net list having the transistor level by using a design rule, and generally comprises three processings: (1) transistor placement; (2) a wiring between transistors; and (3) compaction. A cell synthesis method or a placement wiring method having the transistor level has conventionally been studied vigorously. However, most of these studies have great restrictions on an input circuit, a placement style of transistors and the like in order to simplify computer processings.
As an example of the restrictions, a one-dimensional placement model is employed. The one-dimensional placement model has the form in which P type transistors and N Type transistors are each placed in one string with the gate width direction fitting the vertical direction of a cell so that the two rows of P type and N type transistors is placed in parallel with each other in the cell. Since a lot of cells should be prepared for one cell library, transistors used for the cells have recently had various sizes. In the case where the one-dimensional placement model is employed under the circumstances, a rate of the cell which cannot form an optimal layout for a generally determined cell height in the cell library cannot be ignored. Accordingly, when developing a practical cell synthesis system, it is necessary to employ a method which is not restricted to the one-dimensional placement model. `T. Uehara and W. M. vanCleemput, "Optimal Layout of CMOS Logic Cells", 25th ACM/IEEE Trans. Computer Vol. c-30, pp.305-312, May 1981` has proposed that a layout area can be reduced by sharing a diffusion layer between adjacent transistors. After that, there have been proposals including a relation of algorithms which maximize diffusion sharing to paring problems of P-type and N-type transistors. Most of the algorithms have the one-dimensional placement model as a premise.
A small number of methods having no one-dimensional placement model as a premise have been proposed. A method for generating cells variable in size in the vertical direction of the cells by repeatedly placing a pair of P channel region and N channel region in the cell and using a one-dimensional placement in each channel region has also been proposed. It is supposed that this method is more effective in a macro cell than a standard cell. On the other hand, a method which enables to arrange a plurality of transistors in the vertical direction of the cell in each of P and N channel regions into which the cell is divided as well as in the one-dimensional placement, and to change the number of arrangeable transistors depending on a position in the horizontal direction of the cell region has been described in `C. J. Poirier, "Excellerator: Custom CMOS Leaf Cell Layout Generator", IEEE Trans. On Computer Aided Design Vol. 8, No. 7, pp. 744-755, July 1989`. It is supposed that this method is also effective in the standard cell. However, this method has restrictions, for example, directions of transistors should be arranged in the same direction, sizes of the transistors should be uniform and the like so that a degree of freedom equivalent to manual design is not dealt with. A method which also deals with a degree of freedom related to the directions of the transistors has been disclosed in `D. G. Baltus, J. Allen, "SOLO: A Generator of Efficient Layouts From Optimized MOS Circuit Schematics", Design Automation Conference, pp. 445-452, 1988`. According to this method, a cell circuit is divided into partial circuits and a specific placement pattern (gate matrix style) is applied to the partial circuit so that the cell is not always optimized.
As described in `Chi Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu, "An Efficient Layout Style for Two-Metal CMOS Leaf Cells and Its Automatic Synthesis", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 3, pp. 410-424, March 1993`, it is recognized that a cell height should be reduced in the same manner as a cell width in order to optimize a layout. A problem of optimizing a wiring in a cell which is a factor of determining the cell height has become important to transistor placement.
Various methods for optimizing a wiring between elements have been known by studies of optimal placement of a standard cell on a block and the like. Even if these methods are exactly applied to the problem of the transistor placement, a layout of the cell cannot be optimized. In order to optimize the cell while taking a cell width and a cell height into consideration, two optimization indexes, that is, optimization of diffusion and that of wirings by minimization of diffusion separation (maximization of diffusion sharing) should be dealt with at the same time. In the conventional transistor placement method, the two optimization indexes are not taken into consideration at the same time but optimization is divided into two stages in which first optimization is performed by one of the indexes and second optimization is performed by the other index. A typical method has been well known in which a partial circuit is extracted from a given circuit of a cell, transistors are placed in the extracted partial circuit in order to optimize diffusion, results of placement are regarded as transistor groups, and the transistor groups are placed in order to optimize a wiring.
The conventional method has a restriction that P type transistors and N type transistors are arranged vertically in a one-dimensional placement style. Thus, the transistors are placed on a horizontal dot string and the placement is evaluated by using grid coordinates. The above-mentioned document written by C. Y. Hwang has disclosed an example.
In order to apply cell synthesis performed by a computer to actual development of a cell library, it is necessary to solve a problem of a cell area, that is, a problem of how to increase a degree of integration of the cell equivalently to manual layout design. In order to solve this problem, it is necessary to give a complete two-dimensional degree of freedom by a transistor which acts as a placement element in the cell and to optimize a layout of the cell. In the conventional cell synthesis method, however, great restrictions are imposed on an input circuit, a placement style of transistors and the like so as to simplify computer processings as described above. Therefore, the conventional cell synthesis method is inadequate to realize a flexible layout equivalent to manual design.
If the complete two-dimensional degree of freedom is given to the transistors and the transistors are placed by the computer, it takes a lot of time to perform the processing. Therefore, such placement is not practical.
According to the transistor placement method according to the prior art, diffusion and wirings are separately optimized in two stages so that optimal transistor placement cannot always be obtained generally. In particular, the method for extracting partial circuits to group transistors has the following problem. If the number of the transistors of each group is great, a final result of transistor placement greatly depends on selection of the partial circuits. Consequently, there is a high possibility that the final result of placement might be optimized locally. Although a processing efficiency is high, some cells have a variation in a degree of optimization.
In the conventional method, P type transistors and N type transistors are placed on horizontal dot strings and grid coordinates are used to evaluate the placement on the condition that the transistors are vertically arranged in a one-dimensional placement style. According to an actual mask design rule, however, in the case where adjacent transistors share a diffusion electrode, a distance between gates obtained with a contact provided on the electrode is different from that. obtained without the contact provided on the electrode. For this reason, the P type transistors and the N type transistors are not always arranged vertically in a layout obtained after compaction. There is also a possibility that an actual cell might include transistors having different gate lengths. In this case, it is impossible to arrange the P type transistors and the N type transistors vertically. In other words, the conventional transistor placement has a problem that the placement evaluation is not performed in conformity with a real layout.